1. Field of the Invention
The present invention relates generally to a device for generating a bit line selection signal in a semiconductor memory device, and more particularly to a device for generating a bit line selection signal to optimally facilitate the high speed operations of a semiconductor memory device.
2. Description of the Related Art
High-speed and high-integration are the two key technological factors in the modern semiconductor memory design. However, as the memory device is becoming highly integrated, meeting every specification of the speed related parameters is becoming increasingly more difficult. For example, the signal lines in a highly integrated memory device are likely to be elongated more thinly, and this tends to cause more RC delays, making more difficult to meet the the speed related parameters.
Another factor that should not be neglected to meet the speed related parameters in a memory device is to optimally minimize the time required to transfer data from a bit line to a local line in the memory device.
FIG. 1 shows a bit line selection signal generator 102 for use in a memory device to allow transfer of data from bit lines (labeled BIT, /BIT) to local input/output lines (labeled LIO, /LIO). As shown in FIG. 1, a sense amplifier 100 is located between the bit lines BIT, /BIT. The bit lines BIT, /BIT and the local input/output lines LIO, /LIO are separated by column transistors 11, 12.
The gates of the column transistors 11, 12 are connected to a bit line selection signal Yi outputted by a bit line selection signal generator 102. The bit line selection signal Yi enables particular column transistors 11, 12 that correspond to a bit line selected according to a column address inputted to a column decoder 200 as shown in FIG. 2.
Now referring to FIG. 2, the bit line selection signal generator 102 includes the column decoder 200, which has a NAND gate 21 and an inverter 22. The NAND gate 21 receives the column address signal, and the inverter 22 inverts the output signal of the NAND gate 21. Based on the NAND gate 21 output signal, the bit line selection signal Yi is generated. In this regard, the bit line selection signal Yi may be understood also as the column address decoder signal.
The NAND gate 21 and the inverter 22 of FIG. 2 are driven by an external power voltage VEXT, which is also the driving voltage of the memory device itself. Consequently, the voltage of the bit line selection signal Yi, which would enable the column transistors 11, 12, is the same voltage of the VEXT.
One speed related parameter that measures the time taken for a semiconductor memory device to output data in response to a read command is known as tAA. One significant factor that affects the tAA is the driving capacity of the column transistors 11, 12 (FIG. 1). As already discussed, the column transistors 11, 12 are enabled by the bit line selection signal Yi, which is generated by the bit line selection generator 102. As the driving capacity of the column transistors 11, 12 becomes greater, the speed for transmitting data from the bit line BIT, /BIT to a local line LIO, /LIO would be faster.
The external power voltage VEXT, which is the driving voltage for the memory device itself, is typically applied to the gates of the column transistors 11, 12 as the bit line selection signal Yi. The VEXT in a DDR SDRAM is 2.5 V; thus, voltage of the bit line selection signal Yi in a DDR SDRAM is also 2.5 V. Utilizing 2.5 V to enable the column transistors 11, 12 in a DDR SDRAM appears to present no serious technical problems for operating the column transistors 11, 12.
However, technical problems lie in the next-generation semiconductor memory devices, such as DDR2 SDRAM, in which the external power voltage VEXT utilized is below 2.5 V, and more typically less than 1.8 V. Thus, the voltage level of Yi signal in the next generation memory devices applied to the gates of the column transistors would be lower than 1.8 V and cause very poor tAA when it is compared to the tAA of DDR SDRAM.